军团长 • 来自相关话题

5月前

AXI总线协议资料整理

第一部分:1、AXI简介:AXI(Advanced eXtensible Interface)是一种总线协议,该协议是ARM公司提出的AMBA(Advanced Microcontroller Bus Architecture)3.0协议中最重要的部分,是一种 ...查看全部

第一部分:

1、AXI简介:AXIAdvanced eXtensible Interface)是一种总线协议,该协议是ARM公司提出的AMBAAdvanced Microcontroller Bus Architecture3.0协议中最重要的部分,是一种面向高性能、高带宽、低延迟的片内总线。它的地址/控制和数据相位是分离的,支持不对齐的数据传输,同时在突发传输中,只需要首地址,同时分离的读写数据通道、并支持显著传输访问和乱序访问,并更加容易就行时序收敛。AXI AMBA 中一个新的高性能协议。AXI 技术丰富了现有的AMBA 标准内容,满足超高性能和复杂的片上系统(SoC)设计的需求。

2、 AXI 特点: 单向通道体系结构。信息流只以单方向传输,简化时钟域间的桥接,减少门数量。当信号经过复杂的片上系统时,减少延时。   

    支持多项数据交换。通过并行执行猝发操作,极大地提高了数据吞吐能力,可在更短的时间内完成任务,在满足高性能要求的同时,又减少了功耗。   

独立的地址和数据通道。地址和数据通道分开,能对每一个通道进行单独优化,可以根据需要控制时序通道,将时钟频率提到最高,并将延时降到最低。

第二部分:

本部分对AXI1.0协议的各章进行整理。


详细内容请下载该文档

军团长 • 来自相关话题

5月前

a_practical_guide_to_adopting_the_universal_verfication_methodology

What is the Universal Verification Methodology (UVM) 1.1 Verification Planning and Coverage-Driven Verification 1.2 Mult ...查看全部

What is the Universal Verification Methodology (UVM)

 1.1 Verification Planning and Coverage-Driven Verification

 1.2 Multi-Language and Methodologies

 1.3 What is Unique about This Book?

 1.4 How to Use This Book

 1.4.1 How to Run the Examples

 1.4.2 Conventions in This Book

2.1 UVM Testbench and Environments

2.2 Interface UVCs

2.2.1 Data Items

2.2.2 Driver/Bus Functional Model (BFM)

2.2.3 Sequencer.

2.2.4 Monitor

2.2.5 Collector

2.2.6 Agents

2.2.7 The Environment

2.2.8 Testbench

2.3 System and Module UVCs.

2.3.1 Software UVCs

2.4 The SystemVerilog UVM Class Library

2.4.1 UVM Utilities

2.4.1.1 The UVM Factory

2.4.1.2 Transaction-Level Modeling (TLM)

Object-Oriented Programming (OOP)

3.1 Introduction

3.2 Designing Large Software Applications

3.3 What is an Object in OOP?

3.4 Distributed Development Environment

3.5 Separation of Concerns

3.6 Classes, Objects, and Programs

3.7 Using Generalization and Inheritance

3.8 Creating Compact Reusable Code

3.9 Polymorphism in OOP

3.10 Downcast

3.11 Class Libraries

3.12 Static Methods and Attributes

3.13 Parameterized Classes

3.14 Packages and Namespaces.

3.15 Unified Modeling-Language Diagrams

3.16 Software Design Patterns

3.16.1 Software Design Anti-Patterns

3.17 Why Isn’t the Existing OOP Methodology Enough?

3.18 Aspect-Oriented Programming

UVM Library Basks

4.1 Using the UVM Library

4.1.1 Hello World Example

4.1.2 Guidelines for Using the UVM Library

4.2 Library Base Classes

4.3 The uvm_object Class

4.3.1 UVM Field Automation

4.3.2 uvm_object Definition Guidelines

4.3.3 UVM Object Automation Usage Examples

4.3.4 Using UVM Field Automation

4.4 The uvm_component Class

4.4.1 Simulation Phase Methods

4.4.2 Hierarchy Information Functions

4.4.3 uvm_top Component

4.5 UVM Configuration Mechanism

4.6 Transaction-Level Modeling in UVM

4.6.1 Key TLM Concepts in UVM

4.6.1.1 Modeling Transactions

4.6.1.2 TLM Ports and Exports

4.6.1.3 Connecting Ports to Exports

4.6.1.4 Connecting Ports to Ports and Exports to Exports

4.6.1.5 Using uvm_tlm_fifo

4.6.1.6 Analysis Ports and Exports

4.6.1.7 `uvm_*imp_decl Macros

4.7 UVM Factory

4.8 UVM Message Facilities

4.8.1 UVM Message APIs

4.8.2 Guidelines for Using UVM Messages

4.8.3 Modifying Message Verbosity

4.9 Callbacks

4.9.1 Using Callbacks

4.9.1.1 Developer

4.9.1.2 Use

4.9.2 Guidelines for Using Callbacks

 4.9.2.1 Developer Guidelines

 4.9.2.2 User Guidelines.

 4.9.3 The Report Catcher Built-In Callback.

 Interface UVCs

 5.1 Stimulus Modeling and Generation

 5.1.1 Modeling Data Items

 5.1.2 Defining Control Fields

 5.1.3 Inheritance and Constraint Layering

 5.1.4 Using Empty Constraint Blocks for Tests

5.1.5 A Simple Data Item Test.

 5.2 Creating the Driver

 5.2.1 The SystemVerilog Interface and Virtual Interface

 5.3 Creating the Sequencer.

 5.3.1 Key Randomization Requirements

 5.3.2 A Non-UVM Generator

 5.3.3 The UVM Sequencer.

 5.4 Connecting the Driver and Sequencer

 5.4.1 Basic Sequencer and Driver Interaction

5.4.2 Querying for the Randomized Item.

5.4.3 Supporting Pipeline Protocols

5.4.4 Sending Processed Data Back to the Sequencer

5.5 Creating the Collector and Monitor.

5.5.1 Connecting the Collector and Monitor

5.6 Modeling Topology with UVM

5.7 Creating the Agent.

5.7.1 Using connect() to Connect Components

5.7.2 Agent Configuration.

5.8 Creating the UVM Verification Component.

5.8.1 The Environment Class

5.8.2 Point-to-Point Environments.

5.8.3 The UVM Configuration Mechanism

5.8.3.1 Making the UVC Reusable

 5.8.3.2 Configuration Requirements

 5.8.3.3 UVC Configuration Object

 5.8.3.4 Reconfiguring a Device

 5.8.4 Setting the Agent Virtual Interface

 5.9 Creating UVM Sequences

5.9.1 User-Defined Sequences

5.9.1.1 Sequence and Sequence Item Macros

5.9.2 Predefined Sequences

5.9.2.1 uvm_random_sequence

5.9.2.2 uvm_exhaustive_sequence .

5.9.2.3 uvm_simple_sequence

5.10 Configuring the Sequencer’s Default Sequence

5.10.1 Controlling the Sequencer and Generated Sequences

5.10.2 Overriding Sequence Items and Sequences.

5.10.3 Building a Reusable Sequence Library.

5.11 Coordinating End-of-Test

5.11.1 UVM Objection Mechanism

5.11.2 End-of-Test Objection Mechanism Usage

5.11.3 Tracing Objection Information.

5.11.3.1 Querying the Objection Status

5.11.3.2 Trace Objection Information..

5.11.4 Setting Drain Time

 5.11.5 Identifying Lack of Progress

 5.11.5.1 Using the Heartbeat Mechanism.

 5.11.5.2 Heartbeat Example

 5.12 Implementing Protocol-Specific Coverage and Checks

 5.12.1 Placing Coverage Groups.

 5.12.1.1 Transaction Coverage.

 5.12.1.2 Timing-Related Coverage

 5.12.2 Implementing Checks

 5.12.3 Enabling and Disabling Coverage and Checks

 5.12.3.1 Using the checks_enable and coverage_enable Flags

 5.12.3.2 Fine Granularity for Enabling and Disabling

 5.12.4 Implementing Checks and Coverage in Interfaces

 5.13 Handling Reset

 5.13.1 Reset Methodology for Interface UVCs

 5.13.1.1 Propagating a Reset to the Interface UVC

 5.14 Packaging Interface UVCs.

 5.14.1 Interface UVC Directory Structure

 5.14.2 File Naming Conventions

 5.14.3 UVC Packages

6.1 UVC Development Flow

 6.2 Code Generators

 6.3 Compliance Checklist

 6.4 Automated Compliance Checking

7.1 Testbenches and Tests

7.1.1 The Testbench Class

7.1.2 The Test Classes

7.1.2.1 Where Is My Test? .

7.1.2.2 Why Not Use Program Blocks?

7.2 Creating a Simple Testbench

7.2.1 Instantiating UVCs in a Testbench

7.3 Testbench Configuration.

 7.3.1 UVC Configurable Parameters.

 7.3.2 UVC Configuration Mechanism

 7.3.3 Using a Configuration Class

7.4 Creating a Test

7.4.1 Creating the Base Test

 7.4.2 Creating a Test Library Using a Base Test

 7.4.3 Test Selection

 7.5 Creating Meaningful Tests.

 7.5.1 Constraining Data Items

 7.5.1.1 Creating a Test-Specific Frame

 7.5.2 Sequences and Sequencer Control.

 7.5.2.1 Controlling the Number of Sequences Created by uvm_random_sequence.

 7.5.2.2 Creating and Adding a New Sequence.

 7.5.2.3 Creating Nested Sequences.

 7.5.2.4 Setting the Default Sequence

 7.5.2.5 Sequence Libraries and Reuse .

 7.5.2.6 Disabling a Sequencer

 7.5.2.7 Directed-Test Style Interface

 7.6 Virtual Sequencers and Sequences .

 7.6.1 The Virtual Sequencer

 7.6.2 Creating a Virtual Sequence

 7.6.3 Controlling Other Sequencers

 7.6.4 Connecting a Virtual Sequencer to Sub-Sequencers

 7.7 Checking for DUT Correctness

7.7.1 Scoreboards

 7.7.1.1 UART Controller Scoreboard Example

 7.7.1.2 Creating the Scoreboard

 7.7.1.3 Adding TLM Ports to uvm_scoreboard

 7.7.1.4 TLM Write Implementation

 7.7.1.5 Adding the Scoreboard to the Environment.

 7.8 Implementing a Coverage Model

 7.8.1 Selecting a Coverage Method

 7.8.2 Implementing a Functional Coverage Model

7.8.2.1 Enabling and Disabling Coverage

 Stimulus Generation Topics.

 8.1 Fine Control Sequence Generation

 8.2 Executing Multiple Sequences Concurrently.

 8.2.1 Using fork/join and `uvm_do in the Body of a Sequence..

 8.2.2 Starting Several Sequences in Parallel

 8.3 Using p_sequencer

 8.4 Using the pre_body( ) and post_body( ) Methods.

 8.5 Controlling the Arbitration of Items.

 8.6 Interrupt Sequences.

 8.7 Protocol Layering

 8.7.1 Layering of Protocols

 8.7.2 Layering and Sequences.

 8.7.2.1 Layering Inside One Sequencer

 8.7.2.2 Layering of Several Sequencers.

 8.7.3 Styles of Layering.

 8.7.3.1 Basic Layering .

 8.7.3.2 One-to-One, One-to-Many, Many-to-One, Many-to-Many

8.7.3.3 Different Configurations at Pre-Run Generation and Run Time

 8.7.3.4 Timing Control

 8.7.3.5 Data Control...

 8.7.3.6 Controlling Sequences on Multiple Sequencers.

 8.7.4 Using Layered Sequencers Register and Memory Package

9.1 Register-Related Terminology

 9.2 Register Package Overview.

 9.2.1 Register Packages Usage Flow

 9.2.2 uvm_rgm Hook-Up and Data Flow

 9.2.3 The Register Database (RGM_DB)

9.2.4 Randomization and Injection.

 9.2.4.1 The Register Sequencer and Sequences

 9.2.4.2 The Bus Interface UVC

 9.2.5 Monitoring

 9.2.5.1 The Interface UVC Monitor

 9.2.5.2 The Module UVC.

 9.3 Using the uvm_rgm Package

 9.3.1 Defining the Register and Memory Models..

 9.3.2 Creating an IP-XACT File

9.3.2.1 XML Structure

 9.3.2.2 IP-XACT Structure

 9.3.2.3 IP-XACT Vendor Extensions.

 9.3.2.4 Leveraging XML and IP-XACT Editors

 9.3.2.5 Building the Register-Model Procedurally

 9.3.3 Creating uvm_rgm SystemVerilog Classes.

 9.3.3.1 Using the IP-XACT Utility

 9.3.3.2 The Generated SystemVerilog Code

 9.3.3 Extending the Auto-Generated uvm_rgm Classes..

 9.4 Connecting uvm_rgm Components in a Testbench.

 9.4.1 Connecting Register Components to a Testbench.

 9.4.2 Adding the Necessary Infrastructure to the Bus Master Sequencer.

 9.4.3 Instantiation and Connection to the Testbench

 9.4.4 Reset Handling.

 9.5 Controlling Register Scenarios.

 9.5.1 Register Operations.

9.5.2 Register Read/Write Sequences.

 9.5.2.1 Read-Modify-Write Sequence

 5.9.3 Multi-Register Sequence Operations.

 9.5.4 Sequences Reuse

 9.6 Using uvm_rgm for Checking.

 9.6.1 Using the Shadow Model for Checking

 9.6.2 Advanced Register Checking.

 9.6.2.1 Get Register Functions

 9.7 Updating the Register Database Model.

 9.7.1 Updating the Module UVC

9.8 Collecting Coverage of Register Activities

 9.8.1 Using uvm_rgm Automatic Coverage Facilities

 9.8.2 User-Defined Coverage.

 9.9 Controlling Coverage-Sampling Time

System UVCs and Testbench Infearation

10.1 Introduction

10.2 Module and System UVC Architecture

10.2.1 Reuse in Module and System UVCs

10.2.2 Module UVC Architecture

10.2.3 System UVC Architecture

10.3 Sub-Components of Module and System UVCs.

 10.3.1 Monitor

10.3.1.1 Scoreboard

10.3.1.2 Coverage

10.3.1.3 Reference Model

10.3.2 Memory Blocks and Register Files

10.3.3 Active Stand-In Mode

10.3.4 The Module UVC Class.

10.4 Module UVC Configuration

10.4.1 Standard Configuration Modes




军团长 • 来自相关话题

5月前

3.0_PCIE-PHY_Interface_for_the_PCI_Express_Architecture

Preface1.1 Scope of this Revision1.2 Revision History2 Introduction2.1 PCI Express PHY Layer3 PHY/MAC Interface4 PCI Express PHY F ...查看全部

Preface

1.1 Scope of this Revision

1.2 Revision History

2 Introduction

2.1 PCI Express PHY Layer

3 PHY/MAC Interface

4 PCI Express PHY Functionality

4.1 Transmitter Block Diagram (2.5 and 5.0 GT/s)

4.2 Transmitter Block Diagram (8.0 GT/s)

4.3 Receiver Block Diagram (2.5 and 5.0 GT/s)

4.4 Receiver Block Diagram (8.0 GT/s)

4.5 Clocking

5 PIPE Interface Signal Descriptions

5.1 PHY/MAC Interface Signals

5.2 External Signals

6 PIPE Operational Behavior

6.1 Clocking

6.2 Reset

6.3 Power Management

6.4 Changing Signaling Rate

6.4.1 Fixed data path implementations

6.4.2 Fixed PCLK implementations

6.5 Transmitter Margining

6.6 Selectable De-emphasis

6.7 Receiver Detection

6.8 Transmitting a beacon

6.9 Detecting a beacon

6.10 Clock Tolerance Compensation

6.11 Error Detection

6.11.1 8B/10B Decode Errors

6.11.2 Disparity Errors

6.11.3 Elastic Buffer Errors.

6.12 Loopback

6.13 Polarity Inversion

6.14 Setting negative disparity

6.15 Electrical Idle

6.16 Implementation specific timing and selectable parameter support

6.17 Control Signal Decode table

6.18 Required synchronous signal timings

7 Sample Operational Sequences

7.1 Active PM L0 to L0s and back to L0.

7.2 Active PM to L1 and back to L0

7.3 Receivers and Electrical Idle

7.4 Using CLKREQ# with PIPE

8 Multi-lane PIPE