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2019年07月25日 阅读1033


IC验证--Systemverilog之assetionVCS/Verdi实战

    最近top level的同事提了验证需求,让我在RTL中加assert coverage,开始懵逼,后来查阅一些资料和代码,很快上手了。 这里用一个小例子记录一下,免得日后忘记了。先上代码:
//tb_top.sv的内容:
module tb_top();
reg clk, rst;
wire [3:0] out;
always #5 clk=~clk;
initial
begin
rst=1'b0;
clk=1'b0;
#30;
rst=1'b1;
#150;
$finish;
end
always@(out)
$display('counter is %d',out);
counter(.reset(rst),
.clk(clk),
.q(out));
endmodule
module counter(reset,clk,q);
input reset,clk;
output[3:0] q;
reg[3:0]q;
reg[3:0]count;
always@(posedge clk)
if(!reset) q<=4'b0;
else if(q==4'b1111)
q<=4'b0;
else
q<=q+1;
property p1;
@ (posedge clk) (q[0]|-> ##5 q[3]);
endproperty
a1: assert property(p1)
$display('succeed! time=%t',$time);
else
$display('failure! time=%t',$time);
;
c1: cover property(p1);
endmodule
这里是编译仿真以及查看覆盖率的命令们: r> vcs -sverilog -R -fsdb -ucli -do run_vcs.tcl -cm line+branch+assert tb_top.sv
urg -dir simv.vdb
verdi -workMode hardwareDebug -ssf counter.fsdb -f test_coverage.f
dve -cov -dir ./simv.vdb
verdi -cov -covdir ./simv.vdb
log 结果是:
ucli% run
counter is 0
counter is 1
counter is 2
counter is 3
counter is 4
counter is 5
counter is 6
counter is 7
'tb_top.sv', 41: tb_top.counter.a1: started at 45s failed at 95s
Offending 'q[3]'
failure! time= 95
counter is 8
counter is 9
succeed! time= 115
counter is 10
counter is 11
succeed! time= 135
counter is 12
counter is 13
succeed! time= 155
counter is 14
counter is 15
succeed! time= 175
$finish called from file 'tb_top.sv', line 14.
$finish at simulation time 180
'tb_top.sv', 41: tb_top.counter.a1: started at 165s notfinished
'tb_top.sv', 41: tb_top.counter.a1: started at 145s not finished
'tb_top.sv', 46: tb_top.counter.c1: started at 165s not finished
'tb_top.sv', 46: tb_top.counter.c1: started at 145s not finished
'tb_top.sv', 46: tb_top.counter.c1, 18 attempts, 4 match
---------------------------------------------------------------------------
  VCS Coverage Metrics: during simulation line, branch was monitored
先看波形,可以看到和log对应,95ns处fail, 115,135,155,175ns处成功触发了assertion的内容。后面天蓝色线表示145/165ns处开始但是还没有结束的监测。

亮.jpg

run_vcs.tcl 的内容是:
config timebase 1ns
scope tb_top
run 1ns
call \$fsdbDumpfile(\'counter.fsdb\');
call \$fsdbDumpvars(0,tb_top);
call \$fsdbDumpSVA;
# Run to completion
run
quit
注意,这里 “call \$fsdbDumpSVA;”表示控制dump SVA的东西到fsdb文件去,如果没有这一句,波形文件counter.fsdb里面就不会有a1/c1 .
所有的控制fsdb dump方式都有两种,这个也不例外,你还可以在TB顶层加如下语句去控制dump SVA的东西:
initial begin
$fsdbDumpSVA;
end
  但是个人不倾向于使用这种方式,因为这样就等于代码过多和EDA工具捆在一起了,看起来不干净,不易读。
  另外再看看coverage 报告:(dve -cov -dir ./simv.vdb),可以看到名字为c1的coverage有被cover到,说明这种序列在此次test中被cover了四次。特别要说明的是,通常assert property() 和 cover property()会成对出现,表示我有这样的信号时序行为要求,如果违规assert就要报错,同时还要求我这种时序行为一定要cover到,没有cover到表示我这种时序行为没有测到,coverage report里会显示没有cover到。所以 cover property()也是要写的,否则assert没有报错并不代表说这种“时序行为”测到了,可能根本没有触发这个序列的第一个条件。

亮2.jpg

  例如我把上面代码中counter更新的逻辑删除,那么counter reset成0 一直保持,那么assetion根本不会报错,因为根本没有触发p1里面的q[0]==1, 下面是log(同时log里能看出来c1根本没有cover到:18 attempts, 0 match):
ucli% run
counter is 0
$finish called from file 'tb_top.sv', line 14.
$finish at simulation time 180
'tb_top.sv', 42: tb_top.counter.c1, 18 attempts, 0 match

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